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OpenSCvx
OpenSCvx/OpenSCvx
Home
Getting Started
Getting Started
Examples
Citation
Users Guide
Users Guide
01 Hello Brachistochrone
02 Drone Racing: Constraints and 3-DOF Dynamics
03 Obstacle Avoidance: 6-DOF Dynamics, Parameters, and Vmap
04 Looking Back: Viewpoint Constraints
05 Visualizing Results
06 Dubin's Car: Conditional Statements and Signal Temporal Logic
07 Multi-Link Arms: Lie Algebra and Propagated States
Examples
Examples
Abstract
Abstract
Brachistochrone
Arm
Arm
Three Link Arm
Car
Car
Dubins Car
Dubins Car Conditional
Dubins Car Disjoint
Dubins Car Stljax
Drone
Drone
Cinema Vp
Dr Double Integrator
Dr Vp
Dr Vp Nodal
Dr Vp Polytope
Drone Racing
Obstacle Avoidance
Obstacle Avoidance Nodal
Obstacle Avoidance Vmap
Realtime
Realtime
Base Problems
Base Problems
Cinema Vp Realtime Base
Drone Racing Realtime Base
Obstacle Avoidance Realtime Base
Cinema Vp Realtime
Drone Racing Realtime
Dubins Car Realtime
Obstacle Avoidance Realtime
Rocket
Rocket
3DoF Pdg
Spacecraft
Spacecraft
Proxops Cw
Reference
Reference
config
discretization
discretization
discretization
expert
expert
byof
lowering
validation
init
init
interpolation
integrators
integrators
runge_kutta
lowered
lowered
cvxpy_constraints
cvxpy_variables
dynamics
jax_constraints
parameters
problem
unified
plotting
plotting
plotting
scp_iteration
viser
viser
animated
plotly_integration
primitives
scp
server
problem
propagation
propagation
post_processing
propagation
solvers
solvers
base
ptr_solver
symbolic
symbolic
augmentation
builder
constraint_set
expr
expr
arithmetic
array
constraint
control
expr
lie
lie
adjoint
se3
so3
linalg
logic
math
spatial
state
stl
variable
vmap
hashing
lower
lowerers
lowerers
cvxpy
cvxpy
arithmetic
array
constraint
control
expr
linalg
logic
math
state
jax
jax
arithmetic
array
constraint
control
expr
lie
linalg
logic
logic
Table of contents
logic
math
spatial
state
stl
vmap
preprocessing
problem
time
unified
utils
utils
cache
caching
printing
profiling
utils
Foundations
Foundations
Optimal Control Problem
Isoperimetric Constraint Reformulation
Control Parameterization
Time Dilation
Exact Discretization
Under the Hood
Under the Hood
Lowering Architecture
Table of contents
logic
logic
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